1. Field of the Invention
The present invention relates to a method and apparatus for adjusting a phase of an internal clock signal, and more particularly to a method and apparatus for adjusting an internal clock signal to have the same phase as an external clock signal.
2. Description of Related Art
A first conventional example of a phase adjusting circuit is shown in FIG. 1. Referring to FIG. 1, an external clock signal 1 is inputted to an input terminal 1 of a phase determining circuit 2 of a clock signal generating circuit 3 for phase determination. An output signal 4 of the clock signal generating circuit 3 is separately outputted onto two paths and is supplied to a first selecting circuit 7 and a second selecting circuit 10. The first selecting circuit 7 is a circuit for stopping an internal clock signal 13 in response to an internal clock signal stop control signal 6. The internal clock signal stop control signal 6 is a selection control signal to control the first selecting circuit 7. A first buffer section 11 composed of buffer circuits for the internal clock signal 13 is a section for buffering the internal clock signal 13 which can drive a large load component.
It is necessary that the delay between the output signal 4 of the clock signal generating circuit 3 and the internal clock signal 13 is the same as the delay between the output signal 4 of the clock signal generating circuit 3 and a feed-back clock signal 14. For this reason, there are provided the second selecting circuit 10 which has the same delay as the first selecting circuit 7 and a buffer section 12 composed of buffer circuits which is equivalent to the first buffer section 11. An input terminal of the second selecting circuit 10 for a selection signal 9 is connected to the ground. Accordingly, the second selecting circuit 10 does not function as the selecting circuit and is set to the state in which the output signal 4 of the clock signal generating circuit 3 is always outputted to the buffer section 12.
The feed-back clock signal 14 is supplied to another input terminal of the phase determining circuit 2 of the clock signal generating circuit 3. The phase determining circuit 2 compares the feed-back clock signal 14 and the external clock signal 1 in phase to determine whether the phases are coincident between the feed-back clock signal 14 and the external clock signal 1. It is desirable that the phase of the internal clock signal 13 is coincident with that of the external clock signal 1. However, because the internal clock signal 13 is distributed to the whole of an integrated circuit, a line for the internal clock signal 13 is loaded with a large parasitic capacity. Therefore, the internal clock signal 13 must have the capability to drive the large parasitic capacity and a very large current is consumed when the internal clock signal 13 is activated.
In this manner, the clock signal generating circuit 3 compares the external signal 1 and the feed-back clock signal 14 which has the same delay as the internal clock signal 13 to adjust the phase of the internal clock signal 13. Also, for the above reason, when the internal clock signal 13 is not needed, the internal clock signal 13 is stopped. In this way, reduction of consumption current is adopted.
Further, a time period is necessary for the clock signal generating circuit 3 to adjust the phase of the internal clock signal 13. In a case where the internal clock signal 13 is intermittently activated, the phase adjustment can not follow the internal clock signal and the desired operation can not be satisfied. Therefore, the second selecting circuit 10 and the buffer circuits 12 are provided to generate the feed-back clock signal 14 which has the same phase as the internal clock signal 13 and which always operates. Then, the feed-back clock signal 14 is compared with the external clock signal 1 by the phase determining circuit 2 of the clock signal generating circuit 3 and the phase of the output signal 4 from the clock signal generating circuit is controlled such that a phase difference between the external clock signal 1 and the feed-back clock signal 14 is canceled.
A second conventional example of the clock signal generator which has the structure similar to the abovementioned first conventional example is proposed to Japanese Laid Open Patent Disclosure (JP-A-Heisei 3-217919), as shown in FIG. 2. Referring to FIG. 2, a dummy control signal 59 is provided, which has the same phase as a control signal 56 as an output signal of the output buffer circuit 58, such that the control signal 56 is activated with the same phase as an original external clock signal 52. The dummy control signal 59 and the original control signal 52 are supplied to a phase comparator 66 and the phase of the control signal 56 is adjusted in such a manner that the phase of the original control signal 52 and that of the control signal 56 are coincident with each other.
In the first conventional example, when an external clock signal has a high frequency, it becomes more important for a high-speed operation to cancel a phase difference between the external clock signal and the internal clock signal. This is because the phase difference between the internal clock signal and the external clock signal is a fatal defect since a setup time and a hold time cannot be met in a memory device, in a case where the high-speed data transfer is performed in synchronous with the external clock signal.
In order to solve the above problems, it is necessary that the cancellation of the phase difference between the internal clock signal and the external clock signal is performed with high precision. For this purpose, the cancellation of the phase difference between the internal clock signal and the feed-back clock signal are performed, because the phase difference is equal to the phase difference between the internal clock signal and the feed-back clock signal.
In the above first conventional example, the clock generator is formed in such a manner that the internal clock signal and the feed-back clock signal have the same delay. However, because there is a large difference in parasitic capacity between the internal clock signal and the feed-back clock signal, it is difficult to cancel the phase difference between the internal clock signal and the external clock signal while coping with change of device parameters, change of device temperature and so on.
In the second conventional example, there is also the same problem as the above first conventional example. In the second conventional example, it is described that the dummy control signal 59 has the same phase as the control signal 56. However, because a phase difference is actually present between the dummy control signal 59 and the control signal 56, an operation loss is present in high-speed operation.